Differential via pair impedance verification tool
US6889367B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2003 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Nov 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/0005
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method is disclosed for verifying impedance in a differential via pair. A target differential via pair is identified in a design database. A desired modal characteristic impedance for the target differential via pair is obtained. A two-dimensional window is established around the differential via pair in which neighboring vias will be included in a modal characteristic impedance calculation for the target differential via pair. A modal characteristic impedance for the target differential via pair is calculated based at least in part on the neighboring vias in the two-dimensional window. The target differential via pair is flagged if the calculated modal characteristic impedance does not match the desired modal characteristic impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.