Methods of forming integrated circuits with thermal oxide layers on side walls of gate electrodes wherein the source and drain are higher than the gate electrode
US6890823B2 · kind B2 · utility
14Cited by
8References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2003 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | May 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming thermal oxide layers on a side wall of gate electrodes are disclosed. In particular, thermal oxide layers can be formed on a side wall of a gate electrode by forming a gate electrode on an integrated circuit substrate and forming a thermal oxide layer on a side wall of the gate electrode using a thermal oxidation process. A silicide layer can be formed on the gate electrode after the formation of the thermal oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.