Method of programming electrons onto a floating gate of a non-volatile memory cell
US6891220B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2004 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Jan 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/23
Abstract
A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate, and can be electrically connected to the source region. A method of programming the cell comprises the steps of creating an inversion layer in the second portion of the channel. A stream of electrons is generated at the drain region which is adjacent to the inversion layer, and the stream of electrons is passed through the inversion layer, reaching a pinch off point. The electrons are accelerated through the depletion region…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.