Shift register with reduced area and power consumption
US6891917B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2003 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Aug 4, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shift register device includes transistor pass gates and latches connected in series and disposed along a data bit line, each latch connected to a corresponding transistor pass gate. Each transistor pass gate is controlled by a separate control signal input line that a provides a signal to the transistor pass gate connected to it. The signals are provided in a staggered time pattern beginning with a latch disposed last in succession, shifting data from one position to the next succeeding position. Each latch is capable of storing one bit of data. The shift register utilizes less silicon space while reducing the amount of power consumed during operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.