Method for performing monte-carlo simulations to predict overlay failures in integrated circuit designs
US6892365B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2003 |
| Grant date | May 10, 2005 |
| Priority date | — |
| Expiry date | Sep 22, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of predicting overlay failure of circuit configurations on adjacent, lithographically produced layers of a semiconductor wafer comprises providing design configurations for circuit portions to be lithographically produced on one or more adjacent layers of a semiconductor wafer, and then predicting shape and alignment for each circuit portions on each adjacent layer using one or more predetermined values for process fluctuation or misalignment error. The method then determines dimension of overlap of the predicted shape and alignment of the circuit portions, and compares the determined dimension of overlap to a theoretical minimum to determine whether the predicted dimension of overlap fails. Using different process fluctuation values and misalignment error values, the steps are then iteratively repeated on the provided design configurations to determine whether the predicted dimension of overlap fails, and a report is made of the measure of failures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.