James A. Culp
50Patents
9h-index
86Co-inventors
77Inventor score
Filing activity: Jun 8, 2000 → Jun 6, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6713791B2 | T-RAM array having a planar cell structure and method for fabricating the same | Electricity | 34 | Expired |
| US7536664B2 | Physical design system and method | Physics | 32 | Expired |
| US6429482B1 | Halo-free non-rectifying contact on chip with halo source/drain diffusion | Electricity | 27 | Expired |
| US7865864B2 | Electrically driven optical proximity correction | Physics | 15 | Active |
| US6541166B2 | Method and apparatus for lithographically printing tightly nested and isolated device features using multiple mask exposures | Electricity | 12 | Expired |
| US6996797B1 | Method for verification of resolution enhancement techniques and optical proximity correction in lithography | Emerging Cross-Sectional Technologies | 12 | Expired |
| US7627836B2 | OPC trimming for performance | Physics | 11 | Expired |
| US6892365B2 | Method for performing monte-carlo simulations to predict overlay failures in integrated circuit designs | Physics | 10 | Expired |
| US7269808B2 | Design verification | Physics | 10 | Expired |
| US8473885B2 | Physical design system and method | Physics | 7 | Active |
| US6750109B2 | Halo-free non-rectifying contact on chip with halo source/drain diffusion | Electricity | 7 | Expired |
| US7890906B2 | Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells | Physics | 6 | Active |
| US7900178B2 | Integrated circuit (IC) design method, system and program product | Physics | 6 | Active |
| US9311443B2 | Correcting for stress induced pattern shifts in semiconductor manufacturing | Physics | 5 | Active |
| US7975244B2 | Methodology and system for determining numerical errors in pixel-based imaging simulation in designing lithographic masks | Physics | 5 | Active |
| US8176444B2 | Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance | Physics | 5 | Active |
| US9311442B2 | Net-voltage-aware optical proximity correction (OPC) | Physics | 4 | Active |
| US9836570B1 | Semiconductor layout generation | Emerging Cross-Sectional Technologies | 4 | Active |
| US7503028B2 | Multilayer OPC for design aware manufacturing | Physics | 4 | Active |
| US9075106B2 | Detecting chip alterations with light emission | Physics | 4 | Active |
| US9455186B2 | Selective local metal cap layer formation for improved electromigration behavior | Electricity | 4 | Active |
| US7473648B2 | Double exposure double resist layer process for forming gate patterns | Electricity | 4 | Active |
| US7849433B2 | Integrated circuit with uniform polysilicon perimeter density, method and design structure | Physics | 4 | Active |
| US8239790B2 | Methods and system for analysis and management of parametric yield | Physics | 3 | Active |
| US7669175B2 | Methodology to improve turnaround for integrated circuit design using geometrical hierarchy | Emerging Cross-Sectional Technologies | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.