Substrate topography compensation at mask design: 3D OPC topography anchored
US6893800B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2002 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Jan 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/0035
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A semiconductor manufacturing method analyzes topography variations in three dimensions for each photolithographic level and determines critical dimension (CD) bias compensation as inputs to mask layout creation. Accurate predictions of topography variation for a specific mask design are made at the die level using known pattern density and CMP planarization length characteristics for a specific pattern. Exhaustive characterization of the photoresist response to de-focus and mask bias is determined by artificially expanding loss of CD through focus. Mask compensation to an expanded range of focus over all lines and spaces is maintained within the specification. 3D mask density data is obtained to determine the height component at each pixel location in the die. The resulting 3D OPC model is then utilized for mask creation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.