Scott Jessen
33Patents
7h-index
47Co-inventors
69Inventor score
Filing activity: Jul 2, 1999 → Oct 13, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6893800B2 | Substrate topography compensation at mask design: 3D OPC topography anchored | Physics | 42 | Expired |
| US6258610A | Method analyzing a semiconductor surface using line width metrology with auto-correlation operation | Electricity | 34 | Expired |
| US6225639A | Method of monitoring a patterned transfer process using line width metrology | Electricity | 23 | Expired |
| US7512928B2 | Sub-resolution assist feature to improve symmetry for contact hole lithography | Physics | 9 | Active |
| US6879046B2 | Split barrier layer including nitrogen-containing portion and oxygen-containing portion | Emerging Cross-Sectional Technologies | 9 | Expired |
| US6798043B2 | Structure and method for isolating porous low-k dielectric films | Electricity | 9 | Expired |
| US7067419B2 | Mask layer and dual damascene interconnect structure in a semiconductor device | Electricity | 7 | Expired |
| US9054214B1 | Methodology of forming CMOS gates on the secondary axis using double-patterning technique | Electricity | 7 | Active |
| US7987436B2 | Sub-resolution assist feature to improve symmetry for contact hole lithography | Physics | 4 | Active |
| US9024450B2 | Two-track cross-connect in double-patterned structure using rectangular via | Electricity | 2 | Active |
| US7745067B2 | Method for performing place-and-route of contacts and vias in technologies with forbidden pitch requirements | Physics | 2 | Active |
| US9305848B2 | Elongated contacts using litho-freeze-litho-etch process | Electricity | 2 | Active |
| US9312170B2 | Metal on elongated contacts | Electricity | 1 | Active |
| US10043714B2 | Elongated contacts using litho-freeze-litho-etch process | Electricity | 1 | Active |
| US9620419B2 | Elongated contacts using litho-freeze-litho-etch process | Electricity | 1 | Active |
| US8580675B2 | Two-track cross-connect in double-patterned structure using rectangular via | Electricity | 1 | Active |
| US11171200B2 | Integrated circuits having dielectric layers including an anti-reflective coating | Electricity | 1 | Active |
| US9117775B2 | Alignment to multiple layers | Electricity | 1 | Active |
| US10199380B2 | SRAM cell with T-shaped contact | Emerging Cross-Sectional Technologies | 0 | Active |
| US7262129B2 | Minimizing resist poisoning in the manufacture of semiconductor devices | Electricity | 0 | Expired |
| US9343332B2 | Alignment to multiple layers | Electricity | 0 | Active |
| US11522043B2 | IC with matched thin film resistors | Electricity | 0 | Active |
| US6627885B1 | Method of focused ion beam pattern transfer using a smart dynamic template | Electricity | 0 | Expired |
| US10163911B2 | SRAM cell with T-shaped contact | Emerging Cross-Sectional Technologies | 0 | Active |
| US10748913B2 | SRAM cell with T-shaped contact | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.