Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide
US6894349B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 22, 2002 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Mar 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/111
Abstract
A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage. The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a surface of the semiconductor body and a gate formed on the insulating layer. In addition, a higher-doped pocket of semiconductor material is formed within the top gate region that has a higher integrated doping than the rest of the top gate region. This higher-doped pocket of semiconductor material does not totally deplete during device operation. Moreover, the gate controls, by field-effect, a flow of current through a channel formed laterally between the source pocket and a nearest point of the extended drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.