Optimized electronic package
US6894382B1 · kind B1 · utility
6Cited by
10References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2004 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Jan 8, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package for use with a printed circuit board is provided. The electronic package includes a ground layer having an upper and lower section, a semiconductor chip, a conductive signal layer and a ground plane having a first section electrically connected to the upper section of the ground layer and a second section substantially planar with said lower section of said ground layer, the second section of the ground plane having an additional area to prevent cracking of a solder connection between the ground layer, the ground plane and the printed circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.