DRAM refresh scheme with flexible frequency for active and standby mode
US6894917B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2003 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Feb 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method and an apparatus for DRAM refresh with different frequencies of refresh for active and standby mode. In addition, this invention utilizes different refresh frequencies during active and standby modes to optimize power dissipation and DRAM data integrity. The refresh frequency during active mode is higher than said refresh frequency during standby mode. The refresh frequency during active mode is higher than the prior art refresh frequency during active mode. The refresh frequency during standby mode is lower than the prior art refresh frequency during standby mode. The higher active mode refresh frequency allows the faster restoration of cell data, which is degraded by capacitive discharge coupling through the selection of adjacent word lines. The low standby mode refresh frequency provides a lower standby power dissipation which compensates for the higher active mode power dissipation caused by the higher active mode refresh frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.