Clock synchronous semiconductor memory device
US6894945B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 8, 2002 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Dec 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An internal clock generating circuit generates internal clock signals at a double speed of an external clock signal in a test mode. An input/output circuit inputs/outputs data in a DDR mode in accordance with the double-speed internal clock signal. Particularly, an output drive signal CLKO has a frequency twice as high as that of the internal clock signal, and a data strobe signal DQS is generated as a signal having a frequency twice as high as that of an external data strobe signal. In such a manner, a semiconductor memory device which inputs and outputs data in a DDR mode at a speed twice as fast as that of an external clock signal can be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.