Memory addressing for a virtual machine implementation on a computer processor supporting virtual hash-page-table searching
US6895491B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2002 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | May 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A software monitor, interposed between the hardware layer of a computer system and one or more guest operating systems, constructs and maintains a guest-physical-address-to-host-physical-address map for each guest operating system, and maintains a virtual memory addressing context for each guest operating system that may include a virtual-hash-page table for each guest operating system, the contents of translation registers for each guest operating system, CPU-specific virtual-memory translations for each guest operating system, and the contents of various status registers. The monitor runs at the highest privilege level provided by the hardware system, intercepting attempts to execute privileged instructions by guest operating systems, and simulates or enhances certain of the privileged instructions related to virtual-memory addressing in order to construct and maintain the guest-physical-address-to-host-physical-address map and to provide each guest operating system with the illusion that the guest operating system is executing as the most privileged process on a virtual machine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.