Multidispatch CPU integrated circuit having virtualized and modular resources and adjustable dispatch priority
US6895497B2 · kind B2 · utility
1Cited by
7References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 6, 2002 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | Jun 28, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple dispatch processor has several instruction fetch units, each for providing a stream of instructions to an instruction decode and dispatch unit. The processor also has an resource allocation unit, and multiple resources such as combined integer and address execution pipelines and floating point execution pipelines. Each instruction decode and dispatch unit requests resources needed to perform an instruction of the resource allocation unit, which arbitrates among the multiple instruction decode and dispatch units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.