Mux scan cell with delay circuit for reducing hold-time violations
US6895540B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2002 |
| Grant date | May 17, 2005 |
| Priority date | — |
| Expiry date | May 19, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A mux scan cell includes a multiplexer having a first input node for receiving raw data, a second input node for receiving test data, an output node, a selection node, and a delay circuit electrically connected between the second input node and the output node for prolonging a traveling time which the test data takes to travel from the second input node to the output node. The mux scan cell also includes a flip-flop connected to the multiplexer. With the delay circuit, the traveling time of the test data is prolonged such that the traveling time which the test data takes to travel from the second input node to the output node simulates a sum of a traveling time in which the raw data travels through a combinational logic and a traveling time in which the raw data travels from the first input node to the output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.