Method for fabricating an integrated semiconductor configuration with the aid of thermal oxidation, related semiconductor configuration, and related memory unit
US6897112B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 1, 2002 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Dec 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0411
Abstract
A method for fabricating an integrated semiconductor configuration includes generating a polycrystalline layer at a surface of a base layer and doping the polycrystalline layer. An oxide layer is generated at the polycrystalline layer by rapid thermal oxidation so that the polycrystalline layer can be precisely structured. The method further includes structuring the main layer and performing the thermal oxidation at temperatures above 900° C. for less than 65 seconds. The method also includes carrying out the thermal oxidation as an initial processing step (after generating the main layer) at a temperature of at least substantially equal to the temperature for generating the main layer. A related semiconductor configuration and memory unit are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.