Semiconductor device including MOSFET having band-engineered superlattice
US6897472B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Aug 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes a substrate, and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel that, in turn, includes a plurality of stacked groups of layers. The MOSFET may also include source and drain regions laterally adjacent the superlattice channel, and a gate overlying the superlattice channel for causing transport of charge carriers through the superlattice channel in a parallel direction relative to the stacked groups of layers. Each group of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice channel may have a higher charge carrier mobility in the parallel direction than would otherwise occur.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.