Test structure and related methods for evaluating stress-induced voiding
US6897475B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 21, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Jul 5, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2858
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
This disclosure provides, in one aspect, a test structure formed within a semiconductor wafer. In one embodiment, the test structure comprises a plurality of first level bulk metals having varying sizes, where adjacent ones of the plurality of first level bulk metals are coupled together using vias connected to second level thin conductors located therebetween. In addition, the test structure comprises a plurality of second level bulk metals having varying sizes, where adjacent ones of the plurality of second level bulk metals are coupled together using vias connected to first level thin conductors located therebetween. Furthermore, the test structure includes a first level contact pad coupled to a smallest of the plurality of second level bulk metals, and a second level contact pad coupled to a largest of the plurality of first level bulk metals. In such an embodiment, a largest of the second level bulk metals coupled to a smallest of the first level bulk metals. In other aspects, this disclosure provides a method of manufacturing a test structure within a semiconductor wafer, and a method of evaluating stress-induced voiding of metals within a semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.