Integrated capacitor with enhanced capacitance density and method of fabricating same
US6897508B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 23, 2002 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Jan 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
A thin film integrated multilayer capacitor with substantially enhanced capacitance density suitable for Dynamic Random Access Memory (DRAM) and other integrated capacitor applications is formed into a trench or cavity structure with a completely self-aligned atomic layer deposition (ALD) process flow. Each conductor layer is etched with a wet etch to create recesses between the adjacent insulating layers, which recesses are seamlessly filled with dielectric using an ALD process, so that no part of the conductor is ever exposed to ambient atmosphere. Only silicon-based dielectric materials contact the silicon substrate, and the contact area between silicon and the capacitor is minimized both at the top and the bottom. The dielectric layers comprise Al2O3, ZrO2, or HfO2, which is deposited using an ALD process. Capacitance density is greatly enhanced to a C/∈ of above 1500 fF/μ2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.