Multibit non-volatile memory and method
US6897517B2 · kind B2 · utility
129Cited by
12References
13Claims
0Family size
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Key dates
| Filing date | Jun 24, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Jun 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0458
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory is described having a semiconductor substrate of a first conductivity type, a first and a second junction region of a second conductivity type, whereby said first and said second junction region are part of respectively a first and a second bitline. A select gate is provided which is part of a wordline running perpendicular to said first and said second bitline.Read, write and erase functions for each cell make use of only two polysilicon layers which simplifies manufacture and each memory cell has at least two locations for storing a charge representing at least one bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.