Encapsulated semiconductor package free of chip carrier
US6897566B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 2002 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Jun 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00013
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and a method for fabricating the same are proposed. A chip has an active surface, and an opposing non-active surface. A plurality of conductive elements are mounted on the active surface and electrically connected to the chip. A first encapsulant is formed on the active surface of the chip, for encapsulating the active surface and conductive elements, wherein end portions of the conductive elements are exposed to outside of the first encapsulant, and adapted to be recessed in position with respect to an exposed surface of the first encapsulant. A plurality of conductive media are implanted at end portions of the conductive elements, allowing the chip to be electrically connected to an external device by the conductive elements and conductive media. A second encapsulant is formed on the non-active surface of the chip, and cooperates with the first encapsulant to provide mechanical strength for the semiconductor package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.