Graphics processing architecture employing a unified shader
US6897871B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Nov 20, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.