Ferroelectric non-volatile memory device having integral capacitor and gate electrode, and driving method of a ferroelectric non-volatile memory device
US6898105B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 3, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Jun 3, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric non-volatile memory device that allows the coupling ratio to be increased and the effect of voltage distribution to the ferroelectric capacitor to be improved without increasing the area of the gate electrode of a detection MIS field effect transistor is provided. In a memory cell structure, a semiconductor including regions for a source, a channel, and a drain, a gate insulator on the channel region, a floating gate conductor, a ferroelectrics, and an upper electrode conductor are layered in this order. The structure includes a paraelectric capacitor having one end connected to the floating gate conductor and the other end connected to the source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.