Method of programming a flash memory through boosting a voltage level of a source line
US6898126B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Dec 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of programming a flash memory through boosting a voltage level of a source line. The flash memory has n memory cell transistors cascaded in series, a local bit line positioned above the n memory cell transistors, a buried bit line positioned under the n memory cell transistors, and a source line positioned under the buried bit line. The method includes inputting a word line voltage to a control gate of a kth memory cell transistor, and after floating the local bit line, inputting a source line voltage to the source line for inducing an FN tunneling effect inside the kth memory cell transistor through capacitance coupling between the buried bit line and the source line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.