Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation
US6898139B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2004 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Feb 5, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuit memory devices include a memory cell array that is configured to output data bits in parallel at a first data rate. An output circuit is configured to serially output the data bits to an external terminal at the first data rate in a normal mode of operation, and to serially output the data bits to the external terminal at a second data rate that is lower than the first data rate in a test mode of operation. Accordingly, the memory cell array can operate at a first data rate while allowing the output circuit to output data to an external terminal at a second data rate that is lower than the first data rate, in a test mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.