Multiple memory system support through segment assignment
US6898666B1 · kind B1 · utility
5Cited by
3References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2001 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Jul 19, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of increasing computer system bandwidth for computer system having two or more memory complexes is disclosed in which exclusive OR operations are performed on the data from the data regions to generate parity information which is stored in the same single cache pool as the data regions. By using a single cache pool for related data regions, bandwidth and performance are improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.