Method and system for efficiently restoring a processor's execution state following an interrupt caused by an interruptible instruction
US6898696B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1999 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Jun 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for increasing the efficiency of execution in a processor. Instructions are dispatched in instruction groups, wherein if such an instruction group contains an interruptible instruction of a selected type, only one interruptible instruction of the selected type is included in the instruction group. A state of the processor is recorded, associated respectively with each of said dispatched instruction groups. The processor is restored to the recorded state associated with the instruction group containing the interruptible instruction of the selected type causing an interrupt, in response to the interrupt from one of the interruptible instructions of the selected type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.