Hoichi Cheong
36Patents
15h-index
29Co-inventors
77Inventor score
Filing activity: Nov 14, 1994 → Apr 26, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5584013A | Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache | Physics | 70 | Expired |
| US6553480B1 | System and method for managing the execution of instruction groups having multiple executable instructions | Physics | 70 | Expired |
| US5961636A | Checkpoint table for selective instruction flushing in a speculative execution unit | Physics | 67 | Expired |
| US5870582A | Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched | Physics | 58 | Expired |
| US5887161A | Issuing instructions in a processor supporting out-of-order execution | Physics | 40 | Expired |
| US6073211A | Method and system for memory updates within a multiprocessor data processing system | Physics | 39 | Expired |
| US5913048A | Dispatching instructions in a processor supporting out-of-order execution | Physics | 34 | Expired |
| US5974524A | Method and apparatus for reducing the number of rename registers in a processor supporting out-of-order execution | Physics | 28 | Expired |
| US6098167A | Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution | Physics | 26 | Expired |
| US5996085A | Concurrent execution of machine context synchronization operations and non-interruptible instructions | Physics | 24 | Expired |
| US5694573A | Shared L2 support for inclusion property in split L1 data and instruction caches | Physics | 23 | Expired |
| US6308260A | Mechanism for self-initiated instruction issuing and method therefor | Physics | 22 | Expired |
| US5870612A | Method and apparatus for condensed history buffer | Physics | 18 | Expired |
| US5897651A | Information handling system including a direct access set associative cache and method for accessing same | Physics | 16 | Expired |
| US5860014A | Method and apparatus for improved recovery of processor state using history buffer | Physics | 15 | Expired |
| US6070235A | Data processing system and method for capturing history buffer data | Physics | 15 | Expired |
| US6324640A | System and method for dispatching groups of instructions using pipelined register renaming | Physics | 14 | Expired |
| US5533189A | System and method for error correction code generation | Physics | 13 | Expired |
| US6061777A | Apparatus and method for reducing the number of rename registers required in the operation of a processor | Physics | 13 | Expired |
| US5805906A | Method and apparatus for writing information to registers in a data processing system using a number of registers for processing instructions | Physics | 12 | Expired |
| US5875326A | Data processing system and method for completing out-of-order instructions | Physics | 11 | Expired |
| US6986010B2 | Cache lock mechanism with speculative allocation | Physics | 11 | Expired |
| US8930678B2 | Instruction and logic to length decode X86 instructions | Physics | 11 | Active |
| US6898696B1 | Method and system for efficiently restoring a processor's execution state following an interrupt caused by an interruptible instruction | Physics | 10 | Expired |
| US7266648B2 | Cache lock mechanism with speculative allocation | Physics | 10 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.