Method for modifying a chip layout to minimize within-die CD variations caused by flare variations in EUV lithography
US6898781B2 · kind B2 · utility
14Cited by
12References
9Claims
0Family size
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Key dates
| Filing date | Jul 30, 2003 |
| Grant date | May 24, 2005 |
| Priority date | — |
| Expiry date | Jul 30, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method including determining a first flare convolution based on a feature density of projected structures on a substrate layout, determining a second flare convolution based on a mask for a given substrate layout, determining a system flare variation by summing the first flare convolution and the second flare convolution, and determining a critical dimension variation based on the system flare variation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.