Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same

US6900100B2 · kind B2 · utility

Assignee

• ADVANCED ANALOGIC TECHNOLOGIES INCORPORATED · US

Inventors

• Richard K. Williams · Cupertino, US
• Wayne B. Grabowski · Los Altos, US

Key dates

• Filing date: Mar 4, 2004
• Grant date: May 31, 2005
• Expiry date: Mar 4, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/519

Abstract

The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilico…