LDMOS transistors and methods for making the same
US6900101B2 · kind B2 · utility
66Cited by
12References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 13, 2003 |
| Grant date | May 31, 2005 |
| Priority date | — |
| Expiry date | Jun 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
LDMOS transistor devices and fabrication methods are provided, in which additional dopants are provided to region of a substrate near a thick dielectric between the channel and the drain to reduce device resistance without significantly impacting breakdown voltage. The extra dopants are added by implantation prior to formation of the thick dielectric, such as before oxidizing silicon in a LOCOS process or following trench formation and before filling the trench in an STI process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.