Semiconductor device and method of manufacture
US6900105B2 · kind B2 · utility
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12References
1Claims
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Key dates
| Filing date | Aug 2, 2002 |
| Grant date | May 31, 2005 |
| Priority date | — |
| Expiry date | Sep 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/177
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor manufacturing method, an emitter region (211) and a base enhancement region (207) are formed to provide linear voltage, capacitance and low resistance characteristics. In the manufacturing method, a semiconductor device (200) is formed on a silicon substrate layer (101) with an epitaxial layer (203). Trenches (233) are cut into the epitaxial layer (203) and filled with oxide (601) to provide reduced junction capacitance and reduced base resistance. The emitter region (211) and the base enhancement region (207) are simultaneously formed through an anneal process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.