Method and structure for a high voltage junction field effect transistor
US6900506B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2002 |
| Grant date | May 31, 2005 |
| Priority date | — |
| Expiry date | Mar 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/83
Abstract
A method for fabricating a junction field transistor for high-voltage applications. A lightly doped first epitaxial layer is formed on a highly doped substrate. A second epitaxial layer is deposited with a heavier dopant concentration than the first epitaxial layer. The second layer contains a control structure having a plurality of implanted gate regions and a source. A guard ring is formed to isolate the source and the control structure. The combination of the lightly doped first epitaxial layer and the guard ring enable the JFET to be operated with a breakdown voltage in excess of 100 volts. Multiple guard rings may be used to provide a breakdown voltage in excess of 150 volts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.