Semiconductor device with alternate bonding wire arrangement
US6900551B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 7, 2003 |
| Grant date | May 31, 2005 |
| Priority date | — |
| Expiry date | May 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprising a plurality of wires for electrically connecting a plurality of electrode pads arranged on a main surface of a semiconductor chip along one side of the semiconductor chip to a plurality of connecting portions arranged on the main surface of a wiring substrate along one side of the semiconductor chip, respectively, wherein second wires out of the plural wires consisting of first and second wires adjacent to each other have a larger loop height than the first wires, one end portions of the second wires are connected to the electrode pads at positions farther from one side of the semiconductor chip than the one end portions of the first wires, and the other end portions of the second wires are connected to the connecting portions at positions farther from one side of the semiconductor chip than the other end portions of the first wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.