Method and circuitry for phase align detection in multi-clock domain
US6900674B2 · kind B2 · utility
4Cited by
4References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2003 |
| Grant date | May 31, 2005 |
| Priority date | — |
| Expiry date | Feb 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D13/001
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an embodiment, present application describes a system and method to detect the alignment of multiple clocks in multi-clock domains system. In some variations, multiple clocks are derived from one or more reference clocks using various PLLs. The derived clocks maintain frequency relationship with the reference clock. In some variations, a relationship between the frequencies of various clocks is used to generate the alignment signals in the domain of one of the clocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.