Electronic assembly with sandwiched capacitors and methods of manufacture
US6900991B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2001 |
| Grant date | May 31, 2005 |
| Priority date | — |
| Expiry date | May 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.