Circuits and methods for screening for defective memory cells in semiconductor memory devices
US6901014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2003 |
| Grant date | May 31, 2005 |
| Priority date | — |
| Expiry date | May 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuits and methods that enable screening for defective or weak memory cells in a semiconductor memory device. In one aspect, a semiconductor memory device comprises first and second drivers for a SRAM cell. The first driver is connected between a power supply voltage and the cell, which supplies the power supply voltage into the cell in response to a cell power control signal. The second driver is connected between the power supply signal and the cell, which supplies a voltage lower than the power supply voltage into the cell in response to the cell power down signal. A method for screening for defective or weak cells does not require a time for stabilizing a circuit condition after voltage variation to supply the voltage lower than the power supply voltage from a conventional tester because the cell power down signal activates a driver that causes a supply voltage that is lower than the power supply voltage to be loaded directly to the cell, which results in a reduction of the test time for screening defective cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.