High speed software driven emulator comprised of a plurality of emulation processors with a method to allow high speed bulk read/write operation synchronous DRAM while refreshing the memory

US6901359B1 · kind B1 · utility

Assignee

• Quickturn Design Systems, Inc. · US

Inventors

• William F. Beausoleil · Hopewell Junction, US
• R. Bryan Cook · Poughkeepsie, US
• Tak-kwong Ng · Yorktown, US
• Helmut Roth · Stuttgart, DE
• Peter Tannenbaum · Red Hook, US
• Lawrence A. Thomas · West Hurley, US
• Norton J. Tomassetti · Kingston, US

Key dates

• Filing date: Sep 6, 2000
• Grant date: May 31, 2005
• Expiry date: Oct 28, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/331
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A system and method for bulk transfer to and from the SRAMs in which a starting memory address is latched and is then incremented every clock cycle to generate a new memory address. The addresses are decoded and memory requests are pipelined to the SRAM memory, one every clock cycle. When the memory controller detects transfer of the boundary of a predetermined number of clock cycles or words (e.g. 64 words or four clock cycles) the burst mode of data transfer is stopped and the memory controller waits for a “done” signal before resuming another cycle of the burst transfer mode. The memory controller on detecting a request on this address boundary first does a memory refresh followed by a requested operation; e.g. a continuation of the transfer operation.