Internal cache for on chip test data storage

US6901542B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Thomas Bartenstein · Owego, US
• L. Farnsworth · Middlebury, US
• Douglas C. Heaberlin · Underhill, US
• Edward E. Horton, III · Houston, US
• Leendert M. Huisman · South Burlington, US
• Leah Pastel · Saint Johnsbury Center, US
• Glen E. Richard · Burlington, US
• Raymond J. Rosner · Colchester, US
• Francis Woytowich · Vergennes, US

Key dates

• Filing date: Aug 9, 2001
• Grant date: May 31, 2005
• Expiry date: Jun 14, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C29/26
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method of testing a semiconductor device having a memory is disclosed. The method includes selecting a portion of the memory; testing the selected portion of the memory; designating the selected portion of the memory as a designated memory in response to an acceptable testing result; and storing data in the designated portion of the memory for retrieval at a later time. Provision for soft repair of the selected memory is made. Test data can be compressed before being stored in the designated memory.