Integrated circuit and method
US6902939B2 · kind B2 · utility
9Cited by
5References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2002 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Oct 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.