Integrated semiconductor memory and method for reducing leakage currents in an integrated semiconductor

US6903423B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Helmut Fischer · Calw, DE
• Jens Egerer · Birkenfeld, DE

Key dates

• Filing date: May 12, 2004
• Grant date: Jun 7, 2005
• Expiry date: May 12, 2024

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2029/5006
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated semiconductor memory can include a plurality of subcircuit blocks arranged on nonoverlapping area sections. The subcircuit blocks each have a block supply line and a block ground line, which supply individual switching elements of the subcircuit blocks with a voltage. Each block supply line and block ground line is connected to a chip supply line and a chip ground line, which run outside the area sections of the subcircuit blocks. At least one connection between the chip supply line and the block supply line of at least one subcircuit block or between the chip ground line and the block ground line of at least one subcircuit block can be isolated by a switching device. Furthermore, a method for reducing leakage currents in a semiconductor memory, which, depending on the operating state of the semiconductor memory, isolates or connects individual subcircuit blocks of the semiconductor memory from or to a voltage supply.