Floating-body DRAM using write word line for increased retention time
US6903984B1 · kind B1 · utility
112Cited by
2References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2003 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Dec 31, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/711
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM memory cell uses a single transistor to perform the data storage and switching functions of a conventional cell. The transistor has a floating channel body which stores a potential that corresponds to one of two digital data values. The transistor further includes a gate connected to a first word line, a drain connected to a second word line, and a source connected to a bit line. By setting the word and bit lines to specific voltage states, the channel body stores a digital one potential as a result of impact ionization and a digital zero value as a result of forward bias of body-to-source junction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.