Floating point multiplier/accumulator with reduced latency and method thereof
US6904446B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 24, 2001 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | May 18, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49936
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit (10) for multiplying two floating point operands (A and C) while adding or subtracting a third floating point operand (B) removes latency associated with normalization and rounding from a critical speed path for dependent calculations. An intermediate representation of a product and a third operand are selectively shifted to facilitate use of prior unnormalized dependent resultants. Logic circuitry (24, 42) implements a truth table for determining when and how much shifting should be made to intermediate values based upon a resultant of a previous calculation, upon exponents of current operands and an exponent of a previous resultant operand. Normalization and rounding may be subsequently implemented, but at a time when a new cycle operation is not dependent on such operations even if data dependencies exist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.