Low latency inter-reference ordering in a multiple processor system employing a multiple-level inter-node switch
US6904465B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2001 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Apr 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/15
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multiple-processor system in which a commit message is returned to a source processor that requests a memory access operation so as to indicate the apparent completion of the operation includes a multiple-level switch unit linking nodes that contain the processors. The switch unit includes multiple input switches each of which receives messages from multiple nodes, and a set of output switches whose inputs are the outputs of the input switches and whose outputs are the inputs of the nodes. Each switch processes messages in the order in which they are received by the switch and each output switch follows the same rule as the other output switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.