Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors
US6904502B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2003 |
| Grant date | Jun 7, 2005 |
| Priority date | — |
| Expiry date | Dec 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs using a blind invalidate circuit in high-speed memories. In accordance with an embodiment of the present invention, a tag array memory circuit including a plurality of memory bit circuits coupled together to form an n-bit memory cell; and a blind invalidate circuit coupled to a memory bit circuit in the n-bit memory cell, the blind invalidate circuit to clear a bit in the memory bit circuit, if a primary clear bit line is asserted and a received bit value of a right-adjacent memory bit circuit is zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.