Method for processing multiple semiconductor devices for test
US6905891B2 · kind B2 · utility
7Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2002 |
| Grant date | Jun 14, 2005 |
| Priority date | — |
| Expiry date | Feb 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A packaged array (10) having a temporary substrate (20) is used to test a plurality of semiconductor devices (14). In one embodiment, the temporary substrate (20) is an adhesive substrate, such as tape. A support structure (18) may lie over the temporary substrate (20) or be within the temporary substrate (20). The plurality of semiconductor devices (14) lie within an array (16, 6, or 8) and may be tested in parallel. One array or a multiple number of arrays may lie on the packaged array (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.