Wordline gate contact for an MBIT transistor array layout

US6906371B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Daivid SuitWai Ma · Cary, US
• Guenter Gerstmeier · Chapel Hill, US

Key dates

• Filing date: Aug 12, 2002
• Grant date: Jun 14, 2005
• Expiry date: Jan 16, 2023

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/908

Abstract

A DRAM memory unit contains a memory bit (mbit) transistor and a capacitive region for storing charge. The memory is configured to store data as a charge stored by the capacitive region. Each memory unit is accessed by an associated wordline and the data stored by the memory unit is read from an associated bitline connected to the memory unit. The memory units are connected to the associated wordline via a wordline contact and connected to the associated bitline via a bitline contact. The memory units are arranged in memory unit clusters that include multiple memory units having a common bitline contact. The wordline contact is configured to provide for orientation of the wordlines in the memory array independent of the orientation of the bitlines. The wordline contact is also configured to provide for at least one wordline layer separated from the memory unit by a height of the wordline contact. The wordline contact may be further configured to provide an upper wordline layer and a lower wordline layer each being above the bitline relative to the memory unit.