Method to fabricate high-performance NPN transistors in a BiCMOS process
US6906401B2 · kind B2 · utility
15Cited by
0References
9Claims
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Assignee
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Key dates
| Filing date | May 28, 2004 |
| Grant date | Jun 14, 2005 |
| Priority date | — |
| Expiry date | May 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.