Digital signal delay device
US6906569B2 · kind B2 · utility
3Cited by
6References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 10, 2003 |
| Grant date | Jun 14, 2005 |
| Priority date | — |
| Expiry date | Sep 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention relates to a digital signal delay device (101) for converting a signal (IN) into a corresponding delayed signal (OUT), comprising a plurality of signal delay elements (103a, 103b, 103c) connected in series, wherein, as a function of the desired delay of the delayed signal (OUT), the output signal of a particular signal delay element (103a, 103b, 103c) is used for generating the delayed signal (OUT), and wherein the signal delay elements (103a, 103b, 103c) each comprise one single inverter (105, 106, 107) only.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.