Bit line reference circuits for binary and multiple-bit-per-cell memories
US6906951B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 14, 2002 |
| Grant date | Jun 14, 2005 |
| Priority date | — |
| Expiry date | Jun 14, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5645
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Auto-tracking bit line reference schemes generate a “½ cell current” reference by programming reference cells to threshold voltages that are between threshold voltage levels used to represent data. A common word line can control both a selected memory cell and a reference cell to provide a reference current, and differential sense amplifiers can compare a bit line current to reference currents to thereby distinguish data values. Current through other reference cells can be mirrored to pull-up devices to further improve the tracking of the reference line and bit line currents. Embodiments of the invention can be used with binary and multiple-bit-per-cell memories and with a variety of memory array architectures and memory cell structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.